With the advancement of digital technologies in electronic devices, demands for an increase in a capacity of a nonvolatile memory element, reduction in a writing power in the element, reduction in write/readout time of the element, and a longer life of the element have been increasing, for storing data such as images. It is said that, in response to these demands, miniaturization of a FLASH memory using the existing floating gate has a limitation. To meet the demands, nonvolatile memory elements using perovskite materials (e.g., Pr(1-X) CaXMnO3 (PCMO), LaSrMnO 3 (LSMO), GdBaCoXOY (GBCO), etc) have been proposed (Patent document 1). In this technique, the perovskite material is applied with predetermined pulse voltages of different polarities (or unipolar pulse voltages having different pulse voltages) to increase or decrease its resistance value, and utilizing the resulting varied resistance value, the data are converted into the resistance value of the element to be stored.
There are also nonvolatile memory elements which utilize an event that resistance values of transition metal oxide films (NiO, V2O5, ZnO, Nb2O5, TiO2, WO3, or CoO) are varied by application of the pulse voltages (see Patent document 2).
There are also nonvolatile memory elements in which an amorphous oxide (oxide containing one or more elements selected from, for example, Ti, V, Fe, Co, Y, Zr, Nb, Mo, Hf, Ta, W, Ge, and Si) is provided with an Ag electrode or a Cu electrode and Ag or Cu which is an electrode material is ionized to diffuse into a thin film by application of a voltage so that the resistance value of the amorphous oxide is varied (see Patent document 3). By using these resistance variable materials as memory cells, and combining them with transistors for selecting individual memory cells, an operation of the nonvolatile memory element is attained.
Moreover, there are proposed nonvolatile memory elements using a spinel structure oxide which is a typical resistance variable thin film material (see patent document 4). As described later, a problem arises when the resistance value of the resistance variable film is low. To solve the problem, there is proposed a structure in which a high-resistance layer is stacked on a low-resistance resistance variable film (see Patent document 5 and Non-patent document 1).    Patent Document 1: U.S. Pat. No. 6,204,139 Specification    Patent document 2: Japanese Laid-Open Patent Application Publication No. 2004-363604    Patent document 3: Japanese Laid-Open Patent Application Publication No. 2004-342843    Patent document 4: Japanese Laid-Open Patent Application Publication No. 2006-80259    Patent document 5: Japanese Laid-Open Patent Application Publication No. 2005-317976    Non-patent document 1: Applied Physics Letters 2005, 86th edition, 093509 page